The present invention relates the use of thin film deposition technology to create high density interconnects on a conventional printed wiring board substrate. More specifically, the present invention pertains to an improved method for planarizing thin film dielectric layers formed on the substrate surface in preparation for the formation of subsequent layers. The method of the present invention can be used with or without conventional build-up layers (e.g., a planarized dielectric layer deposited over the upper surface of a completed printed wiring board substrate, typically by the substrate manufacturer, that has a corresponding dielectric layer deposited over the lower surface of the substrate to counterbalance the stress of the upper build-up layer) and is useful for high density integrated circuit packaging of single chip, multi-chip, and support components such as resistors and capacitors. The method of the present invention is also useful for creating interconnections on high density daughter boards that carry packaged devices.
The semiconductor industry continues to produce integrated circuits of increasing complexity and increasing density. The increased complexity of some of these integrated circuits has in turn resulted in an increased number of input/output pads on the circuit chips. At the same time, the increased density of the chips has driven the input/output pad pitch downward. The combination of these two trends has been a significant increase in the connector pin wiring density needed to connect the chips to packages that interface the chips with the outside world and interconnect the chips to other integrated circuit devices.
A number of different technologies have been developed to interconnect multiple integrated circuits. One such technology, based on traditional printed wiring board (PWB) technology that found wide use during the period in which integrated circuits were packaged in surface mount devices like quad flat packs (QFPs), is often referred to as MCM-L or laminate MCM technology. MCM-L technology typically uses copper and insulating dielectric material sub-laminates as building blocks to create required interconnect structures. The process of forming a copper conductive pattern on the sub-laminate in MCM-L technology typically includes forming a dry film of photo resist over the copper layer, patterning and developing the photoresist to form an appropriate mask and selectively etching away the unwanted copper thereby leaving the desired patterned conductive layer.
Substrates used in MCM-L technology can be manufactured in large area panels providing efficiencies that lower the costs of production. Interconnect solutions using this technology generally have relatively good performance characteristics because of the copper and low dielectric constant materials (e.g., less than or equal to 4.0) employed. The printed wiring board industry, however, has not kept pace with the advances in semiconductor manufacturing in terms of pad density. As a result, there is a capability gap between semiconductor manufacturers and interconnect printed wiring board manufacturers.
In some applications, two or more pieces of laminate are laminated together to form a final structure. Interconnection between the laminated layers can be provided by through hole mechanical drilling, followed by plating. The drilling process is relatively slow and expensive and can require a large amount of board space. As the number of interconnect pads increases, an increased number of signal layers is often used to form the interconnect structure. Because of these limitations, the conventional printed wiring board technology needs to go to a large number of metal layers (e.g., greater than eight layers) for some of the applications in high density integrated circuit packaging and daughter board fabrication. Utilizing a large number of layers in this context generally increases cost and decreases electrical performance. Also, the pad size limits the wiring density on any given layer with this technology. Thus, MCM-L technology, while useful for some applications, is not capable of providing the connection density required in other applications.
To improve the interconnect density of MCM-L technology, an advanced printed wiring board technology approach called build-up multi-layer has been developed. In this technology a traditional printed wiring board core is the starting point. Standard drilling and plating techniques are used to form vias in the core. From the basic core this conventional build-up approach has many variations. Typically a dielectric layer approximately 50 micrometers thick is laminated to both the top and bottom major surfaces of the conventionally fabricated printed wiring board substrate. Vias are made in the build-up layer by laser ablation, photo mask/plasma etching or other known methods. An electroless seeding step is then done prior to a panel plating step that metalizes both of the upper and lower surfaces. Subsequent masking and wet etching steps then define a desired conductive pattern over the laminated dielectric layers.
This technology offers a large improvement in terms of density over MCM-L technology without build-up layers; however, such build-up boards require multiple layers in order to meet the developing high density packaging and daughter board requirements. Thus this technology still has limitations.
Another conventional approach used to package high density input/output uses thick film (screen printing) over cofired ceramic substrates. This technology is sometimes referred to as MCM-C, cofired ceramic MCM and thick film MCM technology. Basically, MCM-C technology involves rolling a ceramic mix into sheets, drying the sheets, punching the vias, screening the rolled sheet with a metal paste representing the trace pattern on the surface of the ceramic, stacking and laminating all the layers together, then cofiring at a high temperature (e.g., greater than 850.degree. C.) to achieve the desired interconnections.
MCM-C construction has found extensive use in high density and high reliability products where the robustness of the high density interconnect package outweighs the cost considerations. The ability to create a hermetic seal in the ceramic improves the ability to withstand environments not tolerable to conventional printed wiring board technology. While this technology is capable of high density packaging applications (e.g., greater than 1000 pads), it is also very costly. Additionally, performance characteristics, such as signal propagation time, are impacted due to the relatively high dielectric constant (e.g., between 5.0 and 9.0) of the ceramic materials. MCM-C technology provides a higher connection density than some MCM-L technology, but is still not capable of providing the connection density required for some of today's high density interconnect applications.
A third approach which the high density interconnect and packaging industry has moved toward to address these high density interconnect applications uses thin film MCM technology and is sometimes referred to as MCM-D or MCM deposition technology. MCM-D technology includes forming and patterning thin film conductive traces over a common circuit base.
In some applications, MCM-D technology utilizes a low cost, large surface area printed wiring board structure, with or without the use of the conventional build-up multi-layers on the printed wiring board, as the common circuit base and as a starting point to meet the high density and low cost interconnect requirements. Such large substrates may have a surface area of 40 cm.times.40 cm or more, thereby providing efficiencies that lower the costs of production. This combination of existing conventional high volume printed wiring board technology and advanced thin film deposition technology represents a significant economic advantage and density improvement as compared to the previously discussed MCM-L and MCM-C methods.
One significant feature of MCM-D technology is that it creates a high interconnect density substrate using thin film processes on only one side of the common circuit base. The high density interconnects are formed by depositing alternating conducting and insulating thin film layers. The total thickness of several of these deposited layers is less than the thickness of a single conventional build-up layer. This eliminates the need for balancing the build-up layers on both top and bottom to prevent warpage of the substrate.
The MCM-D process involves first laying down a layer of an insulating dielectric on the top surface of a common circuit base, depositing a conductive material over the dielectric layer, creating a circuit pattern in the conductive material, then depositing the next insulating and conductive layers. The various layers so created are connected through vias constructed using a variety of known techniques such as wet chemical etch, photo expose and develop or laser ablation. In this way a three dimensional deposited laminated structure is achieved enabling high density interconnect patterns to be fabricated in small physical areas.
Despite the definite advantages of MCM-D technology, there are potential problems that may result in failure modes and performance limitations if the thin film formation is not properly implemented. One important aspect of proper thin film layer formation is achieving sufficient planarization. The surface of a typical high density interconnect printed wiring board substrate has relatively coarse features. For example, vertical heights of the plated through hole are often about 35 microns above the substrate surface. At the same time, the space between these surface features may be as small as 0.14 or 0.15 millimeters in some areas of the substrate and may be significantly greater than this in other areas. This creates a deep trench with a low aspect ratio which must be leveled, or planarized, in order to make effective use of the thin film deposition technology for the deposited laminated layers.
A number of different problems either arise from or are exacerbated by improper or insufficient planarization. For example, insufficient planarization may lead to cracking of one or more of the thin film dielectric layers (a problem particularly acute at the interface between the laminated substrate and first thin film layer and alignment problems during subsequent photolithography steps among other problems. These problems tend to be magnified when two or more thin film conductive layers are formed over the laminated substrate.
There have been numerous methods developed over time to achieve a satisfactory planarization of these thin film dielectric layers. These methods include mechanical polishing, extrusion deposition, extrusion deposition combined with spinning, dual coating methods, squeegee techniques, the use of high viscosity dielectrics, tenting using thermal set materials, curtain coating, meniscus coating, roller coating and combinations of some of the above. Mechanical polishing, while fast, generally lacks accuracy. Extrusion methods have had some success, but uniformity continues to be a problem and is very sensitive to viscosity. An alternative is to extrude the dielectric, then add a spin cycle. Although the result is somewhat improved, it still does not provide the requisite level of planarity. Tenting techniques have also been somewhat successful but suffer from both lack of control and relatively high stress created as the result of thick dielectric requirements.
Current known roller coating methods do not allow coatings to be sufficiently thin for thin film deposition. Meniscus coating, while potentially adequate, suffers from very low throughput making it inappropriate for production environments. Various spraying methods of high viscosity materials have been used but the lack of uniformity due to temperature sensitivity and viscosity control issues continues to plague these methods.
Accordingly, improved planarization methods are desirable for thin film MCM-D technology.